CULLEN COLLEGE OF ENGINEERING

University of Houston Cullen College of Engineering

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Industry Group Funding Professor’s Integrated Circuit Research

By: 

Toby Weber
Brankovic
Brankovic

A semiconductor industry group has awarded an $80,000 grant to a University of Houston Cullen College of Engineering professor to develop a new way to connect transistors in integrated circuits (ICs), which are at the heart of practically every electronic device.

The grant comes from the Semiconductor Research Corp., a research consortium whose membership includes many of the world’s largest technology companies, including Intel, Texas Instruments and IBM. Receiving the grant is Stanko Brankovic, associate professor of electrical and computer engineering.

In most integrated circuits, trenches formed between individual transistors are filled with a conducting material, often copper, through a technique known as superconformal electrodeposition. The copper in these trenches allows electricity to flow between transistors.

For the current generation of ICs, the trenches have cross-sections measuring about 40 nanometers. At this size, fabricators can spur the growth of the individual grains of copper and improve their electrical properties through a heat treatment process known as annealing.

The generation of ICs currently under development has trenches with crosssections that measure just 10 to 15 nanometers. At this level, the energy balance between the surface energy of the copper grains and their internal energy prevents the growth of the copper grains, making annealing ineffective.

As a result, the interfaces (or boundaries) between individual grains of copper that make up the interconnects are not very dense, resulting in a high resistivity to the flow of electricity. What’s more, the electricity that does flow through these interconnects literally pushes the copper atoms out of place (a phenomenon known as electromigration), leading to breaks in connections and chip failure.

Brankovic, then, is developing a technique he’s dubbed strained annealing. "What we want to do is externally apply some curvature to the whole silicon wafer [out of which ICs are made] so that the copper in the trenches experience compressive strain, and then anneal it," he said.

This strain, said Brankovic, should change the energy balance in 10-15 nm copper structures during annealing. Through this, he expects to improve the structure of the grain boundaries in copper interconnects allowing electricity to flow more easily and making them less susceptible to failure caused by electromigration.

If the initial proof of concept experiments work, Brankovic anticipates receiving additional funding from the research consortium. With this he will conduct more experiments and build a model that predicts how specific temperatures and strain levels affect the growth of copper interconnects.

Ultimately, the research could lead to the creation of ICs that are not just more powerful, but also more reliable, allowing them to be integrated into more devices, said Brankovic.

"If we do improve electrical properties of these interconnects, the new generation of ultra-small high-density chips will have a lifecycle that is long enough to be appropriate for products sold to the consumer market," he said.

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